1. Field of the Invention
Example embodiments of the present invention relate to systems, apparatuses and methods for synchronizing clock signals, for example, semiconductor devices for synchronizing clock signals in a digital system, and methods for the same.
2. Description of the Related Art
In related art digital systems using a serial interface, a strobe clock signal may be synchronized with a data clock signal. A phase lock loop (PLL) or an inverter delay may be used as an apparatus for synchronizing the strobe clock signal with the data clock signal. To synchronize the strobe clock signal with the data clock signal, at least one of the strobe clock signal and the data clock signal may be delayed for a given time (hereinafter, referred to as the “delay”).
The PLL may control the delay; however, it may also consume more power than the inverter delay. The inverter delay may consume less power than the PLL, however, the inverter delay may not control the delay as accurately. In addition, the delay by the inverter delay may vary depending on the change in process, temperature and/or voltage.
Power consumption may be important in mobile communications terminals such as mobile phones, personal digital assistants (PDAs) or any other handheld consumer electronic device.